EEE 413 Verilog HDL: Modeling, Simulation and Synthesis

This course is designed to cover a global understanding of Verilog HDL- based design.  Topics treated include: Event-Driven Simulation, hardware modeling and simulation in Verilog, data types and logic system in Verilog, Structural and behavioral modeling, user-defined tasks and functions in Verilog and interactive debugging in Verilog using software tools.


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