EEE 414 Advanced VLSI Chip Design Methodology and Optimization using HDL

This course discusses high-tech VLSI chip design area and a flourishing field within Electronic Design Automation. Course covers advanced VLSI chip design methodology which includes physical design, system partitioning, FPGA partitioning, partitioning methods, estimating ASIC size, floorplaning, placement, physical design flow, global routing, detailed routing, special routing, circuit extraction and DRC, scan-chain insertion, clock-tree routing and signal-net routing. The course introduces the systematic top-down design methodology to design complex digital hardware such as FPGA, EPLD and ASIC.  Verilog Hardware Description Language and sophisticated EDA tools are utilized to elaborate the material covered throughout the course. Course projects of this course will lead to open research topics